Turánszki János
686 lines
16 KiB
C++
686 lines
16 KiB
C++
#pragma once
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#include "CommonInclude.h"
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#include <memory>
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#include <vector>
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namespace wiGraphics
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{
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struct Shader;
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struct BlendState;
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struct RasterizerState;
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struct DepthStencilState;
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struct InputLayout;
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struct GPUResource;
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struct GPUBuffer;
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struct Texture;
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enum SHADERSTAGE
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{
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VS,
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HS,
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DS,
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GS,
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PS,
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CS,
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SHADERSTAGE_COUNT
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};
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enum PRIMITIVETOPOLOGY
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{
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UNDEFINED,
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TRIANGLELIST,
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TRIANGLESTRIP,
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POINTLIST,
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LINELIST,
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LINESTRIP,
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PATCHLIST,
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};
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enum COMPARISON_FUNC
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{
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COMPARISON_NEVER,
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COMPARISON_LESS,
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COMPARISON_EQUAL,
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COMPARISON_LESS_EQUAL,
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COMPARISON_GREATER,
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COMPARISON_NOT_EQUAL,
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COMPARISON_GREATER_EQUAL,
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COMPARISON_ALWAYS,
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};
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enum DEPTH_WRITE_MASK
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{
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DEPTH_WRITE_MASK_ZERO,
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DEPTH_WRITE_MASK_ALL,
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};
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enum STENCIL_OP
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{
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STENCIL_OP_KEEP,
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STENCIL_OP_ZERO,
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STENCIL_OP_REPLACE,
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STENCIL_OP_INCR_SAT,
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STENCIL_OP_DECR_SAT,
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STENCIL_OP_INVERT,
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STENCIL_OP_INCR,
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STENCIL_OP_DECR,
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};
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enum BLEND
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{
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BLEND_ZERO,
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BLEND_ONE,
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BLEND_SRC_COLOR,
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BLEND_INV_SRC_COLOR,
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BLEND_SRC_ALPHA,
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BLEND_INV_SRC_ALPHA,
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BLEND_DEST_ALPHA,
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BLEND_INV_DEST_ALPHA,
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BLEND_DEST_COLOR,
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BLEND_INV_DEST_COLOR,
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BLEND_SRC_ALPHA_SAT,
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BLEND_BLEND_FACTOR,
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BLEND_INV_BLEND_FACTOR,
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BLEND_SRC1_COLOR,
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BLEND_INV_SRC1_COLOR,
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BLEND_SRC1_ALPHA,
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BLEND_INV_SRC1_ALPHA,
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};
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enum COLOR_WRITE_ENABLE
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{
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COLOR_WRITE_DISABLE = 0,
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COLOR_WRITE_ENABLE_RED = 1,
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COLOR_WRITE_ENABLE_GREEN = 2,
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COLOR_WRITE_ENABLE_BLUE = 4,
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COLOR_WRITE_ENABLE_ALPHA = 8,
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COLOR_WRITE_ENABLE_ALL = (((COLOR_WRITE_ENABLE_RED | COLOR_WRITE_ENABLE_GREEN) | COLOR_WRITE_ENABLE_BLUE) | COLOR_WRITE_ENABLE_ALPHA)
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};
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enum BLEND_OP
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{
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BLEND_OP_ADD,
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BLEND_OP_SUBTRACT,
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BLEND_OP_REV_SUBTRACT,
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BLEND_OP_MIN,
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BLEND_OP_MAX,
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};
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enum FILL_MODE
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{
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FILL_WIREFRAME,
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FILL_SOLID,
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};
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enum CULL_MODE
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{
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CULL_NONE,
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CULL_FRONT,
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CULL_BACK,
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};
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enum INPUT_CLASSIFICATION
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{
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INPUT_PER_VERTEX_DATA,
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INPUT_PER_INSTANCE_DATA,
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};
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enum USAGE
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{
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USAGE_DEFAULT,
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USAGE_IMMUTABLE,
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USAGE_DYNAMIC,
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USAGE_STAGING,
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};
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enum TEXTURE_ADDRESS_MODE
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{
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TEXTURE_ADDRESS_WRAP,
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TEXTURE_ADDRESS_MIRROR,
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TEXTURE_ADDRESS_CLAMP,
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TEXTURE_ADDRESS_BORDER,
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};
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enum FILTER
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{
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FILTER_MIN_MAG_MIP_POINT,
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FILTER_MIN_MAG_POINT_MIP_LINEAR,
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FILTER_MIN_POINT_MAG_LINEAR_MIP_POINT,
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FILTER_MIN_POINT_MAG_MIP_LINEAR,
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FILTER_MIN_LINEAR_MAG_MIP_POINT,
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FILTER_MIN_LINEAR_MAG_POINT_MIP_LINEAR,
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FILTER_MIN_MAG_LINEAR_MIP_POINT,
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FILTER_MIN_MAG_MIP_LINEAR,
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FILTER_ANISOTROPIC,
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FILTER_COMPARISON_MIN_MAG_MIP_POINT,
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FILTER_COMPARISON_MIN_MAG_POINT_MIP_LINEAR,
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FILTER_COMPARISON_MIN_POINT_MAG_LINEAR_MIP_POINT,
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FILTER_COMPARISON_MIN_POINT_MAG_MIP_LINEAR,
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FILTER_COMPARISON_MIN_LINEAR_MAG_MIP_POINT,
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FILTER_COMPARISON_MIN_LINEAR_MAG_POINT_MIP_LINEAR,
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FILTER_COMPARISON_MIN_MAG_LINEAR_MIP_POINT,
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FILTER_COMPARISON_MIN_MAG_MIP_LINEAR,
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FILTER_COMPARISON_ANISOTROPIC,
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FILTER_MINIMUM_MIN_MAG_MIP_POINT,
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FILTER_MINIMUM_MIN_MAG_POINT_MIP_LINEAR,
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FILTER_MINIMUM_MIN_POINT_MAG_LINEAR_MIP_POINT,
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FILTER_MINIMUM_MIN_POINT_MAG_MIP_LINEAR,
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FILTER_MINIMUM_MIN_LINEAR_MAG_MIP_POINT,
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FILTER_MINIMUM_MIN_LINEAR_MAG_POINT_MIP_LINEAR,
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FILTER_MINIMUM_MIN_MAG_LINEAR_MIP_POINT,
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FILTER_MINIMUM_MIN_MAG_MIP_LINEAR,
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FILTER_MINIMUM_ANISOTROPIC,
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FILTER_MAXIMUM_MIN_MAG_MIP_POINT,
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FILTER_MAXIMUM_MIN_MAG_POINT_MIP_LINEAR,
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FILTER_MAXIMUM_MIN_POINT_MAG_LINEAR_MIP_POINT,
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FILTER_MAXIMUM_MIN_POINT_MAG_MIP_LINEAR,
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FILTER_MAXIMUM_MIN_LINEAR_MAG_MIP_POINT,
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FILTER_MAXIMUM_MIN_LINEAR_MAG_POINT_MIP_LINEAR,
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FILTER_MAXIMUM_MIN_MAG_LINEAR_MIP_POINT,
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FILTER_MAXIMUM_MIN_MAG_MIP_LINEAR,
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FILTER_MAXIMUM_ANISOTROPIC,
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};
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enum FORMAT
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{
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FORMAT_UNKNOWN,
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FORMAT_R32G32B32A32_FLOAT,
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FORMAT_R32G32B32A32_UINT,
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FORMAT_R32G32B32A32_SINT,
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FORMAT_R32G32B32_FLOAT,
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FORMAT_R32G32B32_UINT,
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FORMAT_R32G32B32_SINT,
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FORMAT_R16G16B16A16_FLOAT,
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FORMAT_R16G16B16A16_UNORM,
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FORMAT_R16G16B16A16_UINT,
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FORMAT_R16G16B16A16_SNORM,
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FORMAT_R16G16B16A16_SINT,
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FORMAT_R32G32_FLOAT,
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FORMAT_R32G32_UINT,
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FORMAT_R32G32_SINT,
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FORMAT_R32G8X24_TYPELESS, // depth + stencil (alias)
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FORMAT_D32_FLOAT_S8X24_UINT, // depth + stencil
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FORMAT_R10G10B10A2_UNORM,
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FORMAT_R10G10B10A2_UINT,
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FORMAT_R11G11B10_FLOAT,
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FORMAT_R8G8B8A8_UNORM,
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FORMAT_R8G8B8A8_UNORM_SRGB,
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FORMAT_R8G8B8A8_UINT,
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FORMAT_R8G8B8A8_SNORM,
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FORMAT_R8G8B8A8_SINT,
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FORMAT_B8G8R8A8_UNORM,
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FORMAT_B8G8R8A8_UNORM_SRGB,
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FORMAT_R16G16_FLOAT,
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FORMAT_R16G16_UNORM,
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FORMAT_R16G16_UINT,
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FORMAT_R16G16_SNORM,
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FORMAT_R16G16_SINT,
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FORMAT_R32_TYPELESS, // depth (alias)
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FORMAT_D32_FLOAT, // depth
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FORMAT_R32_FLOAT,
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FORMAT_R32_UINT,
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FORMAT_R32_SINT,
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FORMAT_R24G8_TYPELESS, // depth + stencil (alias)
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FORMAT_D24_UNORM_S8_UINT, // depth + stencil
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FORMAT_R8G8_UNORM,
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FORMAT_R8G8_UINT,
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FORMAT_R8G8_SNORM,
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FORMAT_R8G8_SINT,
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FORMAT_R16_TYPELESS, // depth (alias)
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FORMAT_R16_FLOAT,
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FORMAT_D16_UNORM, // depth
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FORMAT_R16_UNORM,
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FORMAT_R16_UINT,
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FORMAT_R16_SNORM,
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FORMAT_R16_SINT,
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FORMAT_R8_UNORM,
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FORMAT_R8_UINT,
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FORMAT_R8_SNORM,
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FORMAT_R8_SINT,
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FORMAT_BC1_UNORM,
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FORMAT_BC1_UNORM_SRGB,
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FORMAT_BC2_UNORM,
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FORMAT_BC2_UNORM_SRGB,
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FORMAT_BC3_UNORM,
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FORMAT_BC3_UNORM_SRGB,
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FORMAT_BC4_UNORM,
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FORMAT_BC4_SNORM,
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FORMAT_BC5_UNORM,
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FORMAT_BC5_SNORM,
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FORMAT_BC6H_UF16,
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FORMAT_BC6H_SF16,
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FORMAT_BC7_UNORM,
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FORMAT_BC7_UNORM_SRGB
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};
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enum GPU_QUERY_TYPE
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{
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GPU_QUERY_TYPE_INVALID, // do not use! Indicates if query was not created.
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GPU_QUERY_TYPE_EVENT, // has the GPU reached this point?
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GPU_QUERY_TYPE_OCCLUSION, // how many samples passed depthstencil test?
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GPU_QUERY_TYPE_OCCLUSION_PREDICATE, // are there any samples that passed depthstencil test
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GPU_QUERY_TYPE_TIMESTAMP, // retrieve time point of gpu execution
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GPU_QUERY_TYPE_TIMESTAMP_DISJOINT, // timestamp frequency information
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};
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enum INDEXBUFFER_FORMAT
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{
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INDEXFORMAT_16BIT,
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INDEXFORMAT_32BIT,
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};
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enum SUBRESOURCE_TYPE
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{
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SRV,
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UAV,
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RTV,
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DSV,
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};
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enum IMAGE_LAYOUT
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{
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IMAGE_LAYOUT_UNDEFINED, // discard contents
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IMAGE_LAYOUT_GENERAL, // supports everything
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IMAGE_LAYOUT_RENDERTARGET, // render target, write enabled
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IMAGE_LAYOUT_DEPTHSTENCIL, // depth stencil, write enabled
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IMAGE_LAYOUT_DEPTHSTENCIL_READONLY, // depth stencil, read only
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IMAGE_LAYOUT_SHADER_RESOURCE, // shader resource, read only
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IMAGE_LAYOUT_UNORDERED_ACCESS, // shader resource, write enabled
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IMAGE_LAYOUT_COPY_SRC, // copy from
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IMAGE_LAYOUT_COPY_DST, // copy to
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};
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enum BUFFER_STATE
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{
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BUFFER_STATE_GENERAL, // supports everything
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BUFFER_STATE_VERTEX_BUFFER, // vertex buffer, read only
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BUFFER_STATE_INDEX_BUFFER, // index buffer, read only
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BUFFER_STATE_CONSTANT_BUFFER, // constant buffer, read only
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BUFFER_STATE_INDIRECT_ARGUMENT, // argument buffer to DrawIndirect() or DispatchIndirect()
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BUFFER_STATE_SHADER_RESOURCE, // shader resource, read only
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BUFFER_STATE_UNORDERED_ACCESS, // shader resource, write enabled
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BUFFER_STATE_COPY_SRC, // copy from
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BUFFER_STATE_COPY_DST, // copy to
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};
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// Flags ////////////////////////////////////////////
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enum BIND_FLAG
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{
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BIND_VERTEX_BUFFER = 0x1L,
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BIND_INDEX_BUFFER = 0x2L,
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BIND_CONSTANT_BUFFER = 0x4L,
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BIND_SHADER_RESOURCE = 0x8L,
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BIND_STREAM_OUTPUT = 0x10L,
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BIND_RENDER_TARGET = 0x20L,
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BIND_DEPTH_STENCIL = 0x40L,
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BIND_UNORDERED_ACCESS = 0x80L,
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};
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enum CPU_ACCESS
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{
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CPU_ACCESS_WRITE = 0x10000L,
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CPU_ACCESS_READ = 0x20000L,
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};
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enum RESOURCE_MISC_FLAG
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{
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RESOURCE_MISC_SHARED = 0x2L,
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RESOURCE_MISC_TEXTURECUBE = 0x4L,
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RESOURCE_MISC_INDIRECT_ARGS = 0x10L,
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RESOURCE_MISC_BUFFER_ALLOW_RAW_VIEWS = 0x20L,
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RESOURCE_MISC_BUFFER_STRUCTURED = 0x40L,
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RESOURCE_MISC_TILED = 0x40000L,
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};
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// Descriptor structs:
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struct Viewport
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{
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float TopLeftX = 0.0f;
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float TopLeftY = 0.0f;
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float Width = 0.0f;
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float Height = 0.0f;
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float MinDepth = 0.0f;
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float MaxDepth = 1.0f;
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};
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struct InputLayoutDesc
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{
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static const uint32_t APPEND_ALIGNED_ELEMENT = 0xffffffff; // automatically figure out AlignedByteOffset depending on Format
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char* SemanticName = nullptr;
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uint32_t SemanticIndex = 0;
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FORMAT Format = FORMAT_UNKNOWN;
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uint32_t InputSlot = 0;
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uint32_t AlignedByteOffset = APPEND_ALIGNED_ELEMENT;
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INPUT_CLASSIFICATION InputSlotClass = INPUT_CLASSIFICATION::INPUT_PER_VERTEX_DATA;
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uint32_t InstanceDataStepRate = 0;
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};
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union ClearValue
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{
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float color[4];
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struct ClearDepthStencil
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{
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float depth;
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uint32_t stencil;
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} depthstencil;
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};
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struct TextureDesc
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{
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enum TEXTURE_TYPE
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{
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TEXTURE_1D,
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TEXTURE_2D,
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TEXTURE_3D,
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} type = TEXTURE_2D;
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uint32_t Width = 0;
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uint32_t Height = 0;
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uint32_t Depth = 0;
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uint32_t ArraySize = 1;
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uint32_t MipLevels = 1;
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FORMAT Format = FORMAT_UNKNOWN;
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uint32_t SampleCount = 1;
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USAGE Usage = USAGE_DEFAULT;
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uint32_t BindFlags = 0;
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uint32_t CPUAccessFlags = 0;
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uint32_t MiscFlags = 0;
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ClearValue clear = {};
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IMAGE_LAYOUT layout = IMAGE_LAYOUT_GENERAL;
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};
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struct SamplerDesc
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{
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FILTER Filter = FILTER_MIN_MAG_MIP_POINT;
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TEXTURE_ADDRESS_MODE AddressU = TEXTURE_ADDRESS_CLAMP;
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TEXTURE_ADDRESS_MODE AddressV = TEXTURE_ADDRESS_CLAMP;
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TEXTURE_ADDRESS_MODE AddressW = TEXTURE_ADDRESS_CLAMP;
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float MipLODBias = 0.0f;
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uint32_t MaxAnisotropy = 0;
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COMPARISON_FUNC ComparisonFunc = COMPARISON_NEVER;
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float BorderColor[4] = { 0.0f,0.0f,0.0f,0.0f };
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float MinLOD = 0.0f;
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float MaxLOD = FLT_MAX;
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};
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struct RasterizerStateDesc
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{
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FILL_MODE FillMode = FILL_SOLID;
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CULL_MODE CullMode = CULL_NONE;
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bool FrontCounterClockwise = false;
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int32_t DepthBias = 0;
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float DepthBiasClamp = 0.0f;
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float SlopeScaledDepthBias = 0.0f;
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bool DepthClipEnable = false;
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bool MultisampleEnable = false;
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bool AntialiasedLineEnable = false;
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bool ConservativeRasterizationEnable = false;
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uint32_t ForcedSampleCount = 0;
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};
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struct DepthStencilOpDesc
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{
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STENCIL_OP StencilFailOp = STENCIL_OP_KEEP;
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STENCIL_OP StencilDepthFailOp = STENCIL_OP_KEEP;
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STENCIL_OP StencilPassOp = STENCIL_OP_KEEP;
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COMPARISON_FUNC StencilFunc = COMPARISON_NEVER;
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};
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struct DepthStencilStateDesc
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{
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bool DepthEnable = false;
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DEPTH_WRITE_MASK DepthWriteMask = DEPTH_WRITE_MASK_ZERO;
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COMPARISON_FUNC DepthFunc = COMPARISON_NEVER;
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bool StencilEnable = false;
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uint8_t StencilReadMask = 0xff;
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uint8_t StencilWriteMask = 0xff;
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DepthStencilOpDesc FrontFace;
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DepthStencilOpDesc BackFace;
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};
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struct RenderTargetBlendStateDesc
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{
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bool BlendEnable = false;
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BLEND SrcBlend = BLEND_SRC_ALPHA;
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BLEND DestBlend = BLEND_INV_SRC_ALPHA;
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BLEND_OP BlendOp = BLEND_OP_ADD;
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BLEND SrcBlendAlpha = BLEND_ONE;
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BLEND DestBlendAlpha = BLEND_ONE;
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BLEND_OP BlendOpAlpha = BLEND_OP_ADD;
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uint8_t RenderTargetWriteMask = COLOR_WRITE_ENABLE_ALL;
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};
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struct BlendStateDesc
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{
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bool AlphaToCoverageEnable = false;
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bool IndependentBlendEnable = false;
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RenderTargetBlendStateDesc RenderTarget[8];
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};
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struct GPUBufferDesc
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{
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uint32_t ByteWidth = 0;
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USAGE Usage = USAGE_DEFAULT;
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uint32_t BindFlags = 0;
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uint32_t CPUAccessFlags = 0;
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uint32_t MiscFlags = 0;
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uint32_t StructureByteStride = 0; // needed for typed and structured buffer types!
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FORMAT Format = FORMAT_UNKNOWN; // only needed for typed buffer!
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};
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struct GPUQueryDesc
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{
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GPU_QUERY_TYPE Type = GPU_QUERY_TYPE_INVALID;
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};
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struct GPUQueryResult
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{
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uint64_t result_passed_sample_count = 0;
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uint64_t result_timestamp = 0;
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uint64_t result_timestamp_frequency = 0;
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};
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struct PipelineStateDesc
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{
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const Shader* vs = nullptr;
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const Shader* ps = nullptr;
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const Shader* hs = nullptr;
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const Shader* ds = nullptr;
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const Shader* gs = nullptr;
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const BlendState* bs = nullptr;
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const RasterizerState* rs = nullptr;
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const DepthStencilState* dss = nullptr;
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const InputLayout* il = nullptr;
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PRIMITIVETOPOLOGY pt = TRIANGLELIST;
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uint32_t sampleMask = 0xFFFFFFFF;
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};
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struct GPUBarrier
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{
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enum TYPE
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{
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MEMORY_BARRIER, // UAV accesses
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IMAGE_BARRIER, // image layout transition
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BUFFER_BARRIER, // buffer state transition
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} type = MEMORY_BARRIER;
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union
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{
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struct Memory
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{
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const GPUResource* resource;
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} memory;
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struct Image
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{
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const Texture* texture;
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IMAGE_LAYOUT layout_before;
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IMAGE_LAYOUT layout_after;
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} image;
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struct Buffer
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{
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const GPUBuffer* buffer;
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|
BUFFER_STATE state_before;
|
|
BUFFER_STATE state_after;
|
|
} buffer;
|
|
};
|
|
|
|
static GPUBarrier Memory(const GPUResource* resource = nullptr)
|
|
{
|
|
GPUBarrier barrier;
|
|
barrier.type = MEMORY_BARRIER;
|
|
barrier.memory.resource = resource;
|
|
return barrier;
|
|
}
|
|
static GPUBarrier Image(const Texture* texture, IMAGE_LAYOUT before, IMAGE_LAYOUT after)
|
|
{
|
|
GPUBarrier barrier;
|
|
barrier.type = IMAGE_BARRIER;
|
|
barrier.image.texture = texture;
|
|
barrier.image.layout_before = before;
|
|
barrier.image.layout_after = after;
|
|
return barrier;
|
|
}
|
|
static GPUBarrier Buffer(const GPUBuffer* buffer, BUFFER_STATE before, BUFFER_STATE after)
|
|
{
|
|
GPUBarrier barrier;
|
|
barrier.type = BUFFER_BARRIER;
|
|
barrier.buffer.buffer = buffer;
|
|
barrier.buffer.state_before = before;
|
|
barrier.buffer.state_after = after;
|
|
return barrier;
|
|
}
|
|
};
|
|
struct RenderPassAttachment
|
|
{
|
|
enum TYPE
|
|
{
|
|
RENDERTARGET,
|
|
DEPTH_STENCIL,
|
|
} type = RENDERTARGET;
|
|
enum LOAD_OPERATION
|
|
{
|
|
LOADOP_LOAD,
|
|
LOADOP_CLEAR,
|
|
LOADOP_DONTCARE,
|
|
} loadop = LOADOP_LOAD;
|
|
const Texture* texture = nullptr;
|
|
int subresource = -1;
|
|
enum STORE_OPERATION
|
|
{
|
|
STOREOP_STORE,
|
|
STOREOP_DONTCARE,
|
|
} storeop = STOREOP_STORE;
|
|
IMAGE_LAYOUT initial_layout = IMAGE_LAYOUT_GENERAL;
|
|
IMAGE_LAYOUT final_layout = IMAGE_LAYOUT_GENERAL;
|
|
};
|
|
struct RenderPassDesc
|
|
{
|
|
uint32_t numAttachments = 0;
|
|
RenderPassAttachment attachments[9] = {};
|
|
};
|
|
struct IndirectDrawArgsInstanced
|
|
{
|
|
uint32_t VertexCountPerInstance = 0;
|
|
uint32_t InstanceCount = 0;
|
|
uint32_t StartVertexLocation = 0;
|
|
uint32_t StartInstanceLocation = 0;
|
|
};
|
|
struct IndirectDrawArgsIndexedInstanced
|
|
{
|
|
uint32_t IndexCountPerInstance = 0;
|
|
uint32_t InstanceCount = 0;
|
|
uint32_t StartIndexLocation = 0;
|
|
int32_t BaseVertexLocation = 0;
|
|
uint32_t StartInstanceLocation = 0;
|
|
};
|
|
struct IndirectDispatchArgs
|
|
{
|
|
uint32_t ThreadGroupCountX = 0;
|
|
uint32_t ThreadGroupCountY = 0;
|
|
uint32_t ThreadGroupCountZ = 0;
|
|
};
|
|
struct SubresourceData
|
|
{
|
|
const void *pSysMem = nullptr;
|
|
uint32_t SysMemPitch = 0;
|
|
uint32_t SysMemSlicePitch = 0;
|
|
};
|
|
struct Rect
|
|
{
|
|
int32_t left = 0;
|
|
int32_t top = 0;
|
|
int32_t right = 0;
|
|
int32_t bottom = 0;
|
|
};
|
|
|
|
|
|
// Resources:
|
|
|
|
struct GraphicsDeviceChild
|
|
{
|
|
std::shared_ptr<void> internal_state;
|
|
inline bool IsValid() const { return internal_state.get() != nullptr; }
|
|
};
|
|
|
|
struct Shader : public GraphicsDeviceChild
|
|
{
|
|
SHADERSTAGE stage = SHADERSTAGE_COUNT;
|
|
std::vector<uint8_t> code;
|
|
};
|
|
|
|
struct Sampler : public GraphicsDeviceChild
|
|
{
|
|
SamplerDesc desc;
|
|
|
|
const SamplerDesc& GetDesc() const { return desc; }
|
|
};
|
|
|
|
struct GPUResource : public GraphicsDeviceChild
|
|
{
|
|
enum class GPU_RESOURCE_TYPE
|
|
{
|
|
BUFFER,
|
|
TEXTURE,
|
|
UNKNOWN_TYPE,
|
|
} type = GPU_RESOURCE_TYPE::UNKNOWN_TYPE;
|
|
inline bool IsTexture() const { return type == GPU_RESOURCE_TYPE::TEXTURE; }
|
|
inline bool IsBuffer() const { return type == GPU_RESOURCE_TYPE::BUFFER; }
|
|
};
|
|
|
|
struct GPUBuffer : public GPUResource
|
|
{
|
|
GPUBufferDesc desc;
|
|
|
|
const GPUBufferDesc& GetDesc() const { return desc; }
|
|
};
|
|
|
|
struct InputLayout : public GraphicsDeviceChild
|
|
{
|
|
std::vector<InputLayoutDesc> desc;
|
|
};
|
|
|
|
struct BlendState : public GraphicsDeviceChild
|
|
{
|
|
BlendStateDesc desc;
|
|
|
|
const BlendStateDesc& GetDesc() const { return desc; }
|
|
};
|
|
|
|
struct DepthStencilState : public GraphicsDeviceChild
|
|
{
|
|
DepthStencilStateDesc desc;
|
|
|
|
const DepthStencilStateDesc& GetDesc() const { return desc; }
|
|
};
|
|
|
|
struct RasterizerState : public GraphicsDeviceChild
|
|
{
|
|
RasterizerStateDesc desc;
|
|
|
|
const RasterizerStateDesc& GetDesc() const { return desc; }
|
|
};
|
|
|
|
struct Texture : public GPUResource
|
|
{
|
|
TextureDesc desc;
|
|
|
|
const TextureDesc& GetDesc() const { return desc; }
|
|
};
|
|
|
|
struct GPUQuery : public GraphicsDeviceChild
|
|
{
|
|
GPUQueryDesc desc;
|
|
|
|
const GPUQueryDesc& GetDesc() const { return desc; }
|
|
};
|
|
|
|
struct PipelineState : public GraphicsDeviceChild
|
|
{
|
|
size_t hash = 0;
|
|
PipelineStateDesc desc;
|
|
|
|
const PipelineStateDesc& GetDesc() const { return desc; }
|
|
};
|
|
|
|
struct RenderPass : public GraphicsDeviceChild
|
|
{
|
|
size_t hash = 0;
|
|
RenderPassDesc desc;
|
|
|
|
const RenderPassDesc& GetDesc() const { return desc; }
|
|
};
|
|
}
|