turanszkij
546 lines
13 KiB
C++
546 lines
13 KiB
C++
#ifndef _GRAPHICS_DESCRIPTORS_H_
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#define _GRAPHICS_DESCRIPTORS_H_
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#include "CommonInclude.h"
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namespace wiGraphics
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{
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struct VertexShader;
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struct PixelShader;
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struct HullShader;
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struct DomainShader;
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struct GeometryShader;
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struct ComputeShader;
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struct BlendState;
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struct RasterizerState;
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struct DepthStencilState;
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struct VertexLayout;
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struct Texture;
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enum SHADERSTAGE
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{
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VS,
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HS,
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DS,
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GS,
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PS,
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CS,
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SHADERSTAGE_COUNT
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};
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enum PRIMITIVETOPOLOGY
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{
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UNDEFINED_TOPOLOGY,
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TRIANGLELIST,
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TRIANGLESTRIP,
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POINTLIST,
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LINELIST,
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PATCHLIST,
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};
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enum COMPARISON_FUNC
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{
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COMPARISON_NEVER,
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COMPARISON_LESS,
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COMPARISON_EQUAL,
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COMPARISON_LESS_EQUAL,
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COMPARISON_GREATER,
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COMPARISON_NOT_EQUAL,
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COMPARISON_GREATER_EQUAL,
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COMPARISON_ALWAYS,
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};
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enum DEPTH_WRITE_MASK
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{
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DEPTH_WRITE_MASK_ZERO,
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DEPTH_WRITE_MASK_ALL,
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};
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enum STENCIL_OP
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{
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STENCIL_OP_KEEP,
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STENCIL_OP_ZERO,
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STENCIL_OP_REPLACE,
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STENCIL_OP_INCR_SAT,
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STENCIL_OP_DECR_SAT,
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STENCIL_OP_INVERT,
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STENCIL_OP_INCR,
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STENCIL_OP_DECR,
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};
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enum BLEND
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{
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BLEND_ZERO,
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BLEND_ONE,
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BLEND_SRC_COLOR,
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BLEND_INV_SRC_COLOR,
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BLEND_SRC_ALPHA,
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BLEND_INV_SRC_ALPHA,
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BLEND_DEST_ALPHA,
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BLEND_INV_DEST_ALPHA,
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BLEND_DEST_COLOR,
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BLEND_INV_DEST_COLOR,
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BLEND_SRC_ALPHA_SAT,
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BLEND_BLEND_FACTOR,
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BLEND_INV_BLEND_FACTOR,
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BLEND_SRC1_COLOR,
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BLEND_INV_SRC1_COLOR,
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BLEND_SRC1_ALPHA,
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BLEND_INV_SRC1_ALPHA,
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};
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enum COLOR_WRITE_ENABLE
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{
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COLOR_WRITE_DISABLE = 0,
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COLOR_WRITE_ENABLE_RED = 1,
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COLOR_WRITE_ENABLE_GREEN = 2,
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COLOR_WRITE_ENABLE_BLUE = 4,
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COLOR_WRITE_ENABLE_ALPHA = 8,
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COLOR_WRITE_ENABLE_ALL = (((COLOR_WRITE_ENABLE_RED | COLOR_WRITE_ENABLE_GREEN) | COLOR_WRITE_ENABLE_BLUE) | COLOR_WRITE_ENABLE_ALPHA)
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};
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enum BLEND_OP
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{
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BLEND_OP_ADD,
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BLEND_OP_SUBTRACT,
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BLEND_OP_REV_SUBTRACT,
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BLEND_OP_MIN,
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BLEND_OP_MAX,
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};
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enum FILL_MODE
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{
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FILL_WIREFRAME,
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FILL_SOLID,
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};
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enum CULL_MODE
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{
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CULL_NONE,
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CULL_FRONT,
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CULL_BACK,
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};
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enum INPUT_CLASSIFICATION
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{
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INPUT_PER_VERTEX_DATA,
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INPUT_PER_INSTANCE_DATA,
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};
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enum USAGE
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{
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USAGE_DEFAULT,
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USAGE_IMMUTABLE,
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USAGE_DYNAMIC,
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USAGE_STAGING,
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};
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enum TEXTURE_ADDRESS_MODE
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{
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TEXTURE_ADDRESS_WRAP,
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TEXTURE_ADDRESS_MIRROR,
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TEXTURE_ADDRESS_CLAMP,
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TEXTURE_ADDRESS_BORDER,
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TEXTURE_ADDRESS_MIRROR_ONCE,
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};
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enum FILTER
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{
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FILTER_MIN_MAG_MIP_POINT,
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FILTER_MIN_MAG_POINT_MIP_LINEAR,
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FILTER_MIN_POINT_MAG_LINEAR_MIP_POINT,
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FILTER_MIN_POINT_MAG_MIP_LINEAR,
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FILTER_MIN_LINEAR_MAG_MIP_POINT,
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FILTER_MIN_LINEAR_MAG_POINT_MIP_LINEAR,
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FILTER_MIN_MAG_LINEAR_MIP_POINT,
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FILTER_MIN_MAG_MIP_LINEAR,
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FILTER_ANISOTROPIC,
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FILTER_COMPARISON_MIN_MAG_MIP_POINT,
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FILTER_COMPARISON_MIN_MAG_POINT_MIP_LINEAR,
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FILTER_COMPARISON_MIN_POINT_MAG_LINEAR_MIP_POINT,
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FILTER_COMPARISON_MIN_POINT_MAG_MIP_LINEAR,
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FILTER_COMPARISON_MIN_LINEAR_MAG_MIP_POINT,
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FILTER_COMPARISON_MIN_LINEAR_MAG_POINT_MIP_LINEAR,
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FILTER_COMPARISON_MIN_MAG_LINEAR_MIP_POINT,
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FILTER_COMPARISON_MIN_MAG_MIP_LINEAR,
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FILTER_COMPARISON_ANISOTROPIC,
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FILTER_MINIMUM_MIN_MAG_MIP_POINT,
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FILTER_MINIMUM_MIN_MAG_POINT_MIP_LINEAR,
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FILTER_MINIMUM_MIN_POINT_MAG_LINEAR_MIP_POINT,
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FILTER_MINIMUM_MIN_POINT_MAG_MIP_LINEAR,
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FILTER_MINIMUM_MIN_LINEAR_MAG_MIP_POINT,
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FILTER_MINIMUM_MIN_LINEAR_MAG_POINT_MIP_LINEAR,
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FILTER_MINIMUM_MIN_MAG_LINEAR_MIP_POINT,
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FILTER_MINIMUM_MIN_MAG_MIP_LINEAR,
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FILTER_MINIMUM_ANISOTROPIC,
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FILTER_MAXIMUM_MIN_MAG_MIP_POINT,
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FILTER_MAXIMUM_MIN_MAG_POINT_MIP_LINEAR,
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FILTER_MAXIMUM_MIN_POINT_MAG_LINEAR_MIP_POINT,
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FILTER_MAXIMUM_MIN_POINT_MAG_MIP_LINEAR,
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FILTER_MAXIMUM_MIN_LINEAR_MAG_MIP_POINT,
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FILTER_MAXIMUM_MIN_LINEAR_MAG_POINT_MIP_LINEAR,
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FILTER_MAXIMUM_MIN_MAG_LINEAR_MIP_POINT,
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FILTER_MAXIMUM_MIN_MAG_MIP_LINEAR,
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FILTER_MAXIMUM_ANISOTROPIC,
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};
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enum FORMAT
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{
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FORMAT_UNKNOWN,
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FORMAT_R32G32B32A32_TYPELESS,
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FORMAT_R32G32B32A32_FLOAT,
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FORMAT_R32G32B32A32_UINT,
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FORMAT_R32G32B32A32_SINT,
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FORMAT_R32G32B32_TYPELESS,
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FORMAT_R32G32B32_FLOAT,
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FORMAT_R32G32B32_UINT,
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FORMAT_R32G32B32_SINT,
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FORMAT_R16G16B16A16_TYPELESS,
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FORMAT_R16G16B16A16_FLOAT,
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FORMAT_R16G16B16A16_UNORM,
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FORMAT_R16G16B16A16_UINT,
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FORMAT_R16G16B16A16_SNORM,
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FORMAT_R16G16B16A16_SINT,
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FORMAT_R32G32_TYPELESS,
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FORMAT_R32G32_FLOAT,
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FORMAT_R32G32_UINT,
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FORMAT_R32G32_SINT,
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FORMAT_R32G8X24_TYPELESS,
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FORMAT_D32_FLOAT_S8X24_UINT,
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FORMAT_R32_FLOAT_X8X24_TYPELESS,
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FORMAT_X32_TYPELESS_G8X24_UINT,
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FORMAT_R10G10B10A2_TYPELESS,
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FORMAT_R10G10B10A2_UNORM,
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FORMAT_R10G10B10A2_UINT,
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FORMAT_R11G11B10_FLOAT,
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FORMAT_R8G8B8A8_TYPELESS,
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FORMAT_R8G8B8A8_UNORM,
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FORMAT_R8G8B8A8_UNORM_SRGB,
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FORMAT_R8G8B8A8_UINT,
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FORMAT_R8G8B8A8_SNORM,
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FORMAT_R8G8B8A8_SINT,
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FORMAT_R16G16_TYPELESS,
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FORMAT_R16G16_FLOAT,
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FORMAT_R16G16_UNORM,
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FORMAT_R16G16_UINT,
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FORMAT_R16G16_SNORM,
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FORMAT_R16G16_SINT,
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FORMAT_R32_TYPELESS,
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FORMAT_D32_FLOAT,
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FORMAT_R32_FLOAT,
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FORMAT_R32_UINT,
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FORMAT_R32_SINT,
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FORMAT_R24G8_TYPELESS,
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FORMAT_D24_UNORM_S8_UINT,
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FORMAT_R24_UNORM_X8_TYPELESS,
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FORMAT_X24_TYPELESS_G8_UINT,
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FORMAT_R8G8_TYPELESS,
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FORMAT_R8G8_UNORM,
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FORMAT_R8G8_UINT,
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FORMAT_R8G8_SNORM,
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FORMAT_R8G8_SINT,
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FORMAT_R16_TYPELESS,
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FORMAT_R16_FLOAT,
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FORMAT_D16_UNORM,
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FORMAT_R16_UNORM,
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FORMAT_R16_UINT,
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FORMAT_R16_SNORM,
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FORMAT_R16_SINT,
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FORMAT_R8_TYPELESS,
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FORMAT_R8_UNORM,
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FORMAT_R8_UINT,
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FORMAT_R8_SNORM,
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FORMAT_R8_SINT,
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FORMAT_A8_UNORM,
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FORMAT_R1_UNORM,
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FORMAT_R9G9B9E5_SHAREDEXP,
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FORMAT_R8G8_B8G8_UNORM,
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FORMAT_G8R8_G8B8_UNORM,
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FORMAT_BC1_TYPELESS,
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FORMAT_BC1_UNORM,
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FORMAT_BC1_UNORM_SRGB,
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FORMAT_BC2_TYPELESS,
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FORMAT_BC2_UNORM,
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FORMAT_BC2_UNORM_SRGB,
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FORMAT_BC3_TYPELESS,
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FORMAT_BC3_UNORM,
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FORMAT_BC3_UNORM_SRGB,
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FORMAT_BC4_TYPELESS,
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FORMAT_BC4_UNORM,
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FORMAT_BC4_SNORM,
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FORMAT_BC5_TYPELESS,
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FORMAT_BC5_UNORM,
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FORMAT_BC5_SNORM,
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FORMAT_B5G6R5_UNORM,
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FORMAT_B5G5R5A1_UNORM,
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FORMAT_B8G8R8A8_UNORM,
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FORMAT_B8G8R8X8_UNORM,
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FORMAT_R10G10B10_XR_BIAS_A2_UNORM,
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FORMAT_B8G8R8A8_TYPELESS,
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FORMAT_B8G8R8A8_UNORM_SRGB,
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FORMAT_B8G8R8X8_TYPELESS,
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FORMAT_B8G8R8X8_UNORM_SRGB,
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FORMAT_BC6H_TYPELESS,
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FORMAT_BC6H_UF16,
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FORMAT_BC6H_SF16,
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FORMAT_BC7_TYPELESS,
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FORMAT_BC7_UNORM,
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FORMAT_BC7_UNORM_SRGB,
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FORMAT_AYUV,
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FORMAT_Y410,
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FORMAT_Y416,
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FORMAT_NV12,
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FORMAT_P010,
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FORMAT_P016,
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FORMAT_420_OPAQUE,
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FORMAT_YUY2,
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FORMAT_Y210,
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FORMAT_Y216,
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FORMAT_NV11,
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FORMAT_AI44,
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FORMAT_IA44,
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FORMAT_P8,
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FORMAT_A8P8,
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FORMAT_B4G4R4A4_UNORM,
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FORMAT_FORCE_UINT = 0xffffffff,
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};
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enum GPU_QUERY_TYPE
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{
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GPU_QUERY_TYPE_EVENT, // has the GPU reached this point?
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GPU_QUERY_TYPE_OCCLUSION, // how many samples passed depthstencil test?
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GPU_QUERY_TYPE_OCCLUSION_PREDICATE, // are there any samples that passed depthstencil test
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GPU_QUERY_TYPE_TIMESTAMP, // retrieve time point of gpu execution
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GPU_QUERY_TYPE_TIMESTAMP_DISJOINT, // timestamp frequency information
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};
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enum INDEXBUFFER_FORMAT
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{
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INDEXFORMAT_16BIT,
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INDEXFORMAT_32BIT,
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};
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// Flags ////////////////////////////////////////////
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enum CLEAR_FLAG
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{
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CLEAR_DEPTH = 0x1L,
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CLEAR_STENCIL = 0x2L,
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};
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enum BIND_FLAG
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{
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BIND_VERTEX_BUFFER = 0x1L,
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BIND_INDEX_BUFFER = 0x2L,
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BIND_CONSTANT_BUFFER = 0x4L,
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BIND_SHADER_RESOURCE = 0x8L,
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BIND_STREAM_OUTPUT = 0x10L,
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BIND_RENDER_TARGET = 0x20L,
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BIND_DEPTH_STENCIL = 0x40L,
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BIND_UNORDERED_ACCESS = 0x80L,
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};
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enum CPU_ACCESS
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{
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CPU_ACCESS_WRITE = 0x10000L,
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CPU_ACCESS_READ = 0x20000L,
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};
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enum RESOURCE_MISC_FLAG
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{
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RESOURCE_MISC_SHARED = 0x2L,
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RESOURCE_MISC_TEXTURECUBE = 0x4L,
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RESOURCE_MISC_DRAWINDIRECT_ARGS = 0x10L,
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RESOURCE_MISC_BUFFER_ALLOW_RAW_VIEWS = 0x20L,
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RESOURCE_MISC_BUFFER_STRUCTURED = 0x40L,
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RESOURCE_MISC_TILED = 0x40000L,
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};
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enum RESOURCE_STATES
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{
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RESOURCE_STATE_COMMON = 0,
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RESOURCE_STATE_VERTEX_AND_CONSTANT_BUFFER = 0x1,
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RESOURCE_STATE_INDEX_BUFFER = 0x2,
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RESOURCE_STATE_RENDER_TARGET = 0x4,
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RESOURCE_STATE_UNORDERED_ACCESS = 0x8,
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RESOURCE_STATE_DEPTH_WRITE = 0x10,
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RESOURCE_STATE_DEPTH_READ = 0x20,
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RESOURCE_STATE_NON_PIXEL_SHADER_RESOURCE = 0x40,
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RESOURCE_STATE_PIXEL_SHADER_RESOURCE = 0x80,
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RESOURCE_STATE_STREAM_OUT = 0x100,
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RESOURCE_STATE_INDIRECT_ARGUMENT = 0x200,
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RESOURCE_STATE_COPY_DEST = 0x400,
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RESOURCE_STATE_COPY_SOURCE = 0x800,
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RESOURCE_STATE_RESOLVE_DEST = 0x1000,
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RESOURCE_STATE_RESOLVE_SOURCE = 0x2000,
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RESOURCE_STATE_GENERIC_READ = (((((0x1 | 0x2) | 0x40) | 0x80) | 0x200) | 0x800),
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RESOURCE_STATE_PRESENT = 0,
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RESOURCE_STATE_PREDICATION = 0x200,
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RESOURCE_STATE_VIDEO_DECODE_READ = 0x10000,
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RESOURCE_STATE_VIDEO_DECODE_WRITE = 0x20000,
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RESOURCE_STATE_VIDEO_PROCESS_READ = 0x40000,
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RESOURCE_STATE_VIDEO_PROCESS_WRITE = 0x80000
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};
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// Structs /////////////////////////////////////////////
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struct ViewPort
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{
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float TopLeftX = 0.0f;
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float TopLeftY = 0.0f;
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float Width = 0.0f;
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float Height = 0.0f;
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float MinDepth = 0.0f;
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float MaxDepth = 1.0f;
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};
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struct VertexLayoutDesc
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{
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static const UINT APPEND_ALIGNED_ELEMENT = 0xffffffff; // automatically figure out AlignedByteOffset depending on Format
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char* SemanticName = nullptr;
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UINT SemanticIndex = 0;
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FORMAT Format = FORMAT_UNKNOWN;
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UINT InputSlot = 0;
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UINT AlignedByteOffset = APPEND_ALIGNED_ELEMENT;
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INPUT_CLASSIFICATION InputSlotClass = INPUT_CLASSIFICATION::INPUT_PER_VERTEX_DATA;
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UINT InstanceDataStepRate = 0;
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};
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struct SampleDesc
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{
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UINT Count = 1;
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UINT Quality = 0;
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};
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struct TextureDesc
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{
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UINT Width = 0;
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UINT Height = 0;
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UINT Depth = 0;
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UINT ArraySize = 1;
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UINT MipLevels = 1;
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FORMAT Format = FORMAT_UNKNOWN;
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SampleDesc SampleDesc;
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USAGE Usage = USAGE_DEFAULT;
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UINT BindFlags = 0;
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UINT CPUAccessFlags = 0;
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UINT MiscFlags = 0;
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};
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struct SamplerDesc
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{
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FILTER Filter = FILTER_MIN_MAG_MIP_POINT;
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TEXTURE_ADDRESS_MODE AddressU = TEXTURE_ADDRESS_CLAMP;
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TEXTURE_ADDRESS_MODE AddressV = TEXTURE_ADDRESS_CLAMP;
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TEXTURE_ADDRESS_MODE AddressW = TEXTURE_ADDRESS_CLAMP;
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float MipLODBias = 0.0f;
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UINT MaxAnisotropy = 0;
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COMPARISON_FUNC ComparisonFunc = COMPARISON_NEVER;
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float BorderColor[4] = { 0.0f,0.0f,0.0f,0.0f };
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float MinLOD = 0.0f;
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float MaxLOD = FLT_MAX;
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};
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struct RasterizerStateDesc
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{
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FILL_MODE FillMode = FILL_SOLID;
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CULL_MODE CullMode = CULL_NONE;
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bool FrontCounterClockwise = false;
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INT DepthBias = 0;
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float DepthBiasClamp = 0.0f;
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float SlopeScaledDepthBias = 0.0f;
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bool DepthClipEnable = false;
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bool MultisampleEnable = false;
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bool AntialiasedLineEnable = false;
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bool ConservativeRasterizationEnable = false;
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UINT ForcedSampleCount = 0;
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};
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struct DepthStencilOpDesc
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{
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STENCIL_OP StencilFailOp = STENCIL_OP_KEEP;
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STENCIL_OP StencilDepthFailOp = STENCIL_OP_KEEP;
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STENCIL_OP StencilPassOp = STENCIL_OP_KEEP;
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COMPARISON_FUNC StencilFunc = COMPARISON_NEVER;
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};
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struct DepthStencilStateDesc
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{
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bool DepthEnable = false;
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DEPTH_WRITE_MASK DepthWriteMask = DEPTH_WRITE_MASK_ZERO;
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COMPARISON_FUNC DepthFunc = COMPARISON_NEVER;
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bool StencilEnable = false;
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UINT8 StencilReadMask = 0xff;
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UINT8 StencilWriteMask = 0xff;
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DepthStencilOpDesc FrontFace;
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DepthStencilOpDesc BackFace;
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};
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struct RenderTargetBlendStateDesc
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{
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bool BlendEnable = false;
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BLEND SrcBlend = BLEND_SRC_ALPHA;
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BLEND DestBlend = BLEND_INV_SRC_ALPHA;
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BLEND_OP BlendOp = BLEND_OP_ADD;
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BLEND SrcBlendAlpha = BLEND_ONE;
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BLEND DestBlendAlpha = BLEND_ONE;
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BLEND_OP BlendOpAlpha = BLEND_OP_ADD;
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UINT8 RenderTargetWriteMask = COLOR_WRITE_ENABLE_ALL;
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};
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struct BlendStateDesc
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{
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bool AlphaToCoverageEnable = false;
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bool IndependentBlendEnable = false;
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RenderTargetBlendStateDesc RenderTarget[8];
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};
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struct GPUBufferDesc
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{
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UINT ByteWidth = 0;
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USAGE Usage = USAGE_DEFAULT;
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UINT BindFlags = 0;
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UINT CPUAccessFlags = 0;
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UINT MiscFlags = 0;
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UINT StructureByteStride = 0; // needed for typed and structured buffer types!
|
|
FORMAT Format = FORMAT_UNKNOWN; // only needed for typed buffer!
|
|
};
|
|
struct GPUQueryDesc
|
|
{
|
|
GPU_QUERY_TYPE Type = GPU_QUERY_TYPE_EVENT;
|
|
};
|
|
struct GPUQueryResult
|
|
{
|
|
BOOL result_passed = FALSE;
|
|
UINT64 result_passed_sample_count = 0;
|
|
UINT64 result_timestamp = 0;
|
|
UINT64 result_timestamp_frequency = 0;
|
|
BOOL result_disjoint = FALSE;
|
|
};
|
|
struct PipelineStateDesc
|
|
{
|
|
const VertexShader* vs = nullptr;
|
|
const PixelShader* ps = nullptr;
|
|
const HullShader* hs = nullptr;
|
|
const DomainShader* ds = nullptr;
|
|
const GeometryShader* gs = nullptr;
|
|
const BlendState* bs = nullptr;
|
|
const RasterizerState* rs = nullptr;
|
|
const DepthStencilState* dss = nullptr;
|
|
const VertexLayout* il = nullptr;
|
|
PRIMITIVETOPOLOGY pt = TRIANGLELIST;
|
|
UINT numRTs = 0;
|
|
FORMAT RTFormats[8] = {};
|
|
FORMAT DSFormat = FORMAT_UNKNOWN;
|
|
SampleDesc sampleDesc;
|
|
UINT sampleMask = 0xFFFFFFFF;
|
|
};
|
|
struct IndirectDrawArgsInstanced
|
|
{
|
|
UINT VertexCountPerInstance = 0;
|
|
UINT InstanceCount = 0;
|
|
UINT StartVertexLocation = 0;
|
|
UINT StartInstanceLocation = 0;
|
|
};
|
|
struct IndirectDrawArgsIndexedInstanced
|
|
{
|
|
UINT IndexCountPerInstance = 0;
|
|
UINT InstanceCount = 0;
|
|
UINT StartIndexLocation = 0;
|
|
INT BaseVertexLocation = 0;
|
|
UINT StartInstanceLocation = 0;
|
|
};
|
|
struct IndirectDispatchArgs
|
|
{
|
|
UINT ThreadGroupCountX = 0;
|
|
UINT ThreadGroupCountY = 0;
|
|
UINT ThreadGroupCountZ = 0;
|
|
};
|
|
struct SubresourceData
|
|
{
|
|
const void *pSysMem = nullptr;
|
|
UINT SysMemPitch = 0;
|
|
UINT SysMemSlicePitch = 0;
|
|
};
|
|
struct Rect
|
|
{
|
|
LONG left = 0;
|
|
LONG top = 0;
|
|
LONG right = 0;
|
|
LONG bottom = 0;
|
|
};
|
|
|
|
}
|
|
|
|
#endif // _GRAPHICS_DESCRIPTORS_H_
|